Axelera Unveils Titania Data Center AIPU Architecture for 2027
Dutch chip startup Axelera AI has disclosed the architecture of Titania, its third-generation AIPU targeting data center inference, with mass production slated for Q3 2027 and over $300 million in orders already booked. Optimized for sparse MoE models, the chip delivers 2.5 PFLOPS at FP8, and a single 4U eight-card server can run a 1.6T MoE model locally, with the company claiming 7x per-watt throughput versus current data center servers.
Related Entities
Full Report
IT之家 November 13 news, Dutch chip startup Axelera AI unveiled the architecture of its third-generation AIPU chip Titania on the 12th local time. It targets the data center inference market, is expected to enter mass production in Q3 2027, and has already secured over $300 million (IT之家 note: approximately 2.006 billion RMB at current exchange rates) in orders.
The Titania chip has a design power consumption of 400W and consists of 2 compute chiplets based on the third-generation D-IMC architecture. It is optimized for sparse MoE models, supports MXPF4 and MXFP8 data formats, and delivers FP8 compute of up to 2.5 PFLOPS; it integrates 128MB of shared SRAM on-chip cache.
In addition, Titania embeds 32 RISC-V cores that can offload host CPU workloads; it also features multi-format codecs such as AV1 and H.265; and the SiP integrates 128GB of LPDDR6 memory with a total bandwidth of 2456GB/s.
At a higher level, Titania supports PCIe AIC and OCP OAM form factors; a 4U eight-card Titania air-cooled server can run a 1.6T MoE model locally at FP4 precision.
Axelera AI states that Titania is expected to achieve 7x the per-watt throughput of current data center-class servers and 1/20 of the total cost of ownership. The per-user speed of a 4U Titania air-cooled server running DeepSeek R1 is sufficient to match NVIDIA's Vera Rubin NVL72 liquid-cooled rack.