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AI CURATED HOT STORY · 11/13/2026

UCIe 4.0 Specification Extends Chiplet Interconnect to System-Level Integration

1 reports archived1 independent sourcesupdated 11/13/2026, 14:53:32
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The UCIe Consortium released version 4.0 of its chiplet interconnect specification, extending the architecture from chip-level interfaces to system-level integration of multiple dies in a unified package. It introduces the UCIe.mem on-package memory link with 93.75% data efficiency and roughly 2.5 TB/s/mm beachfront bandwidth density, plus new power-optimized profiles and enhanced bump designs. The update also adds trusted die state reporting, bidirectional integrity-protected management channels, and automotive-grade reliability extensions.

LATEST/The UCIe Consortium released version 4.0 of its chiplet interconnect specification, extending the architecture from chip-level interfaces to system-level integration of multiple dies in a unified package. It introduces the UCIe.mem on-package memory link with 93.75% data efficiency and roughly 2.5 TB/s/mm beachfront bandwidth density, plus new power-optimized profiles and enhanced bump designs. The update also adds trusted die state reporting, bidirectional integrity-protected management channels, and automotive-grade reliability extensions.

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Total 1 reports · Latest first
  1. IT之家 · IT业界T2·72 pts

    UCIe 4.0 Specification Extends Chiplet Interconnect to System-Level Integration

    • UCIe 4.0 extends interconnect scope from chip-level interfaces to system-level multi-die package integration
    • The UCIe.mem on-package memory link delivers 93.75% data efficiency and about 2.5 TB/s/mm beachfront bandwidth density
    • New power-optimized profiles yield 30-80% efficiency gains at 64GT/s, alongside security and automotive reliability enhancements
UCIe 4.0 Specification Extends Chiplet Interconnect to System-Level Integration | Today for AI