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AI CURATED HOT STORY · 10/29/2026

Qwenputer Embeds Deterministic RISC-V CPU Inside Qwen3.5 Weights

1 reports archived1 independent sourcesupdated 10/29/2026, 08:25:45
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Researcher Divyansh Agrawal introduced Qwenputer, an experimental model embedding a full RISC-V CPU directly into the weights of Qwen 3.5 4B. By utilizing Gated DeltaNet attention layers as RAM, the architecture enables the model to execute arithmetic operations and C/MicroPython code internally during forward passes, eliminating the need for external runtimes or tool calls.

LATEST/Researcher Divyansh Agrawal introduced Qwenputer, an experimental model embedding a full RISC-V CPU directly into the weights of Qwen 3.5 4B. By utilizing Gated DeltaNet attention layers as RAM, the architecture enables the model to execute arithmetic operations and C/MicroPython code internally during forward passes, eliminating the need for external runtimes or tool calls.

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Total 1 reports · Latest first
  1. Hacker News AIT2·88 pts

    Qwenputer Embeds Deterministic RISC-V CPU Inside Qwen3.5 Weights

    • Core innovation involves hard-coding RISC-V CPU instruction sets and state machine logic into neural network weights for purely internal computation.
    • Leverages the linear attention properties of Gated DeltaNet (GDN) layers to simulate Random Access Memory (RAM), overcoming traditional Transformer memory constraints.
    • Follow-up research suggests such hybrid architectures might hide reasoning to evade Chain-of-Thought (CoT) monitoring, while also offering new ideas for building tamper-proof internal oversight tools.