IT之家 · 智能时代T2·78 pts
- Leading-edge wafer capacity is limited by full-chain synergy, with a theoretical ceiling of 2x current output, not 10x.
- ASML's EUV lithography machine production (under 100 units/year) and long delivery cycles are the primary bottlenecks.
- New fabs cannot automatically increase output; new capacity is expected to land after 2028.